Intel MP Specification compatibility

NOTE as of 12/18/2003: While the Intel MP Spec v1.4 is still supported for legacy MP capability and is the simpler mechanism, all new Intel/AMD MP systems have been primarily been designed with ACPI in mind. It's a huge spec that is overcomplex, but it's the way things are going for now if you want complete support covering all the corner cases.

Below this is currently unchanged, but some links have been fixed so the info is still there.

Last (partial) update: Wed 8 AM 4/30/1997.

Contents

• Introduction
• Free OS's supporting the Intel MP Spec
• Example Code/Clarifications of the Spec
• Intel MPS-compatible hardware list

Introduction

My two primary tasks on this topic are: (1) helping to get the SMP code in various free OSes correctly and efficiently supporting this standardized kind of hardware, and (2) Example Code/Clarifications of the Spec, which includes extra documentation.

I don't warrant any of this material, as it is free. I do want to help people out, so please feel free to e-mail me if you have problems with my code/documentation, successes, or just want to comment on it or some related point.

Thanks go to Intel for the use of some equipment for cursory validation and for a few intense debug sessions. This included several different Pentium Pro MP boxes (one with a hardware debugger attached) and a few Pentium MP boxes. Of course all this REALLY means is that it worked on some internal test-bed, but it has been very helpful in finding my stupid mistakes.

My main test machine is currently an Intel Alder with 4 Pentium Pro 150MHz (w/256K L2 cache) CPUs.

Free OS's supporting the Intel MP Spec

Linux has an ongoing SMP project called Linux-SMP, headed by Alan Cox. Configuration is done in the normal fashion, except for uncommenting the "SMP = 1" in the top makefile (if there are multiple CPUs on the machine, it will activate them automatically... if not, then it should still boot and run). Several versions are very stable, and can be used for production work. There's a Linux-SMP status for Intel MPS page, which has been kept reasonably up-to-date on which versions work or not, patches, etc. The status page may go away sometime soon.

FreeBSD has made a lot of progress in the last few months with their FreeBSD Symmeteric MultiProcessor Kernel, much of it done by (I believe, though I'm sure they'll correct me if I'm wrong) Peter Wemm and Steve Passe. The SMP kernel is now merged into the mainline 3.0-current source tree. Important fixes have been made lately that make it much more stable.

Example Code/Clarifications of the Spec

(This will be expanded) Relevant documents are of course the Intel MP Specification itself, the "Multiple Processor Management" sections of both the Pentium and Pentium Pro programmer's/OS writer's guides, the 82489DX User's Manual (AP-388, was part of the "Pentium Processors and Related Products" manual), and finally a general link Intel Developer's Page.

As mentioned above, the spec is really not enough to write an SMP OS. Information on the Intel APIC parts and how to program them must be read through very carefully, plus some errata. Here are a list of features/limitations/results of the spec and APIC documents which may not be obvious from the first read:

• If *only* discrete local APICs (82489DXes) are used up to 255 APICS (and APIC ids from 0 to 254) can be addressed on the APIC bus, otherwise the maximum is 15 (with APIC ids from 0 to 14). This total includes all CPU/local APICs and I/O APICs (i.e. each must have an id).

• There are 2 types of configuration. "Default" and "Configuration Table".:
  • Default Configurations: Many nice properties: (1) Exactly 2 processors, (2) the APIC ids must be 0 & 1 (either can be the bootstrap CPU), (3) APICs are at fixed locations (the local APIC at 0xFEE00000 for each CPU, and the I/O APIC at 0xFEC00000), (4) pre-defined bus and interrupt configurations.

  • Configuration Table Configurations: Table lists all of the data values that are fixed in the "Default" versions. APICs can be at different locations, and the only rule for APIC numbering is that one must have an id of 0 (i.e. they don't have to be consecutive). New capabilities also exist, such as providing information on multiple parallel buses and multiple I/O APIC configurations with independent interrupt routing.

• The bootstrap CPU is not required to be the APIC id #0. This is the case in some machines.

• The bootup configuration of the APICs routes all non-CPU-specific interrupts to the bootstrap CPU only (i.e. until the APICs are reprogrammed).

• Compatibility with multiple versions of the local APICs requires a very intricate CPU startup sequence and some sections of code which very based on this version number. Care can minimize this. Only one fully generic CPU startup sequence can be run at one time (i.e. parallel startup can't be done).

• smp-imps.c
• smp-imps.h
• apic.h

• The license is essentially free for arbitrary non-commercial or commercial use as desired, but if it's not inconvenient, please attribute me appropriately.
• The CPU startup sequence is incomplete, but what part is there should be reasonably correct, as it's similar to what I had put into the Linux kernel some years ago.
• May not work on the 486 SMP machines (this likely doesn't matter at all, since nobody cares any more about them).

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